CSI5V93 - VLSI Design Automation
CSI5V93DA

A Better State-Machine Paper

Here is a better state machine paper.

State Machines from BDDs Expressions and Truth Tables

Posted by Peter M Maurer at 6/25/2008 8:45 AM | Add Comment

Physical Design Automation Papers

Here are some documents about physical design automation.

Basic VLSI Structures
Design Rules
Partitioning
Routing
Channel Routing

Posted by Peter M Maurer at 6/25/2008 6:38 AM | Add Comment

Last three simulation papers

Here are the last of the simulation papers.

State Machine Simulation
Event Driven Simulation without Loops or Conditionals
Using Conjugate Symmetry to Enhance Gate-Level Simulations

Enjoy!

Posted by Peter M Maurer at 6/20/2008 6:23 AM | Add Comment

The first readings for Summer 2008

Here are some chapters of a partially written book on digital simulation. We will be covering these chapters during the first portion of the course.

Chapter 1
Chapter 2
Chapter 3
Chapter 4
Chapter 5
Chapter 6
Chapter 7

Posted by Peter M Maurer at 5/30/2008 10:34 AM | Add Comment

Syllabus Summer 2008

Click Here for the syllabus

Posted by Peter M Maurer at 5/30/2008 10:31 AM | Add Comment

Two final papers

TimberWolf 3

Placement

Posted by Peter M Maurer at 6/27/2007 9:35 AM

Two more papers

Beaver

Global Routing

Posted by Peter M Maurer at 6/26/2007 9:37 AM

More and More papers

The real greedy channel routing paper

The Original Channel Routing Paper.

Hierarchical Channel Routing

More on Partitioning

Switchbox Routing

Posted by Peter M Maurer at 6/22/2007 9:50 AM

Routing and Partitioning readings

Routing

Partitioning

Channel Routing

Basic Channel Routing

Doggleg Channel Routing

Greedy Channel Router

YACR2

River Routing

Over-The-Cell Channel Routing

Posted by Peter M Maurer at 6/21/2007 8:58 AM

Notes for 6-1-07

Click here for the Notes for 6-1-07

Posted by Peter M Maurer at 6/1/2007 10:07 AM
Copyright 2007 Peter M. Maurer. All rights reserved.